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FSYC163D, FSYC163R
Data Sheet May 1999 File Number
4740
Radiation Hardened, SEGR Resistant N-Channel Power MOSFETs
The Discrete Products Operation of Intersil has developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary for military applications have not been sacrificed. The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available. This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. Reliability screening is available as either commercial, TXV equivalent of MIL-S-19500, or Space equivalent of MIL-S-19500. Contact Intersil for any desired deviations from the data sheet.
Features
* 62A, 130V, rDS(ON) = 0.030 * Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) * Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm2 with VDS up to 80% of Rated Breakdown and VGS of 10V Off-Bias * Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM * Photo Current - 12.5nA Per-RAD(Si)/s Typically * Neutron - Maintain Pre-RAD Specifications for 1E13 Neutrons/cm2 - Usable to 1E14 Neutrons/cm2
Symbol
D
G
S
Packaging
SMD2
Ordering Information
RAD LEVEL 10K 10K 100K 100K 100K SCREENING LEVEL Commercial TXV Commercial TXV Space PART NUMBER/BRAND FSYC163D1 FSYC163D3 FSYC163R1 FSYC163R3 FSYC163R4
Formerly available as type TA45203.
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
FSYC163D, FSYC163R
Absolute Maximum Ratings
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Derated Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100H, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . .IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) FSYC163D, FSYC163R 130 130 62 39 186 20 208 83 1.67 186 62 186 -55 to 150 300 UNITS V V A A A V W W W/ oC A A A oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) TEST CONDITIONS ID = 1mA, VGS = 0V VGS = VDS, ID = 1mA TC = -55oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC MIN 130 1.5 0.5 VGS = 0V to 20V VGS = 0V to 12V VGS = 0V to 2V VDD = 65V, ID = 62A ID = 62A, VDS = 15V VDS = 25V, VGS = 0V, f = 1MHz TYP 0.022 170 28 94 8 4300 1300 500 MAX 5.0 4.0 25 250 100 200 1.95 0.030 0.049 50 210 100 45 300 200 8.2 34 120 0.6 UNITS V V V V A A nA nA V ns ns ns ns nC nC nC nC nC V pF pF pF
oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage
Zero Gate Voltage Drain Current
IDSS IGSS VDS(ON) rDS(ON)12 td(ON) tr td(OFF) tf Qg(TOT) Qg(12) Qg(TH) Qgs Qgd V(PLATEAU) CISS COSS CRSS RJC
VDS = 104V, VGS = 0V VGS = 20V VGS = 12V, ID = 62A ID = 39A, VGS = 12V
Gate to Source Leakage Current
Drain to Source On-State Voltage Drain to Source On Resistance
Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate Charge at 12V Threshold Gate Charge Gate Charge Source Gate Charge Drain Plateau Voltage Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case
VDD = 65V, ID = 62A, RL = 1.0, VGS = 12V, RGS = 2.35
4-2
FSYC163D, FSYC163R
Source to Drain Diode Specifications
PARAMETER Forward Voltage Reverse Recovery Time SYMBOL VSD trr ISD = 62A ISD = 62A, dISD/dt = 100A/s TC = 25oC, Unless Otherwise Specified SYMBOL (Note 3) (Note 3) (Notes 2, 3) (Note 3) (Notes 1, 3) (Notes 1, 3) BVDSS VGS(TH) IGSS IDSS VDS(ON) rDS(ON)12 TEST CONDITIONS VGS = 0, ID = 1mA VGS = VDS, ID = 1mA VGS = 20V, VDS = 0V VGS = 0, VDS = 104V VGS = 12V, ID = 62A VGS = 12V, ID = 39A MIN 130 1.5 MAX 4.0 100 25 1.95 0.030 UNITS V V nA A V TEST CONDITIONS MIN 0.6 TYP MAX 1.8 670 UNITS V ns
Electrical Specifications up to 100K RAD
PARAMETER Drain to Source Breakdown Volts Gate to Source Threshold Volts Gate to Body Leakage Zero Gate Leakage Drain to Source On-State Volts Drain to Source On Resistance NOTES: 1. Pulse test, 300s max. 2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS .
Single Event Effects (SEB, SEGR) Note 4
ENVIRONMENT (NOTE 5) TEST Single Event Effects Safe Operating Area SYMBOL SEESOA ION SPECIES Ni Br Br Br Br NOTES: 4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN. 5. Fluence = 1E5 ions/cm2 (typical), T = 25oC. 6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). TYPICAL LET (MeV/mg/cm) 26 37 37 37 37 TYPICAL RANGE () 43 36 36 36 36 APPLIED VGS BIAS (V) -20 -5 -10 -15 -20 (NOTE 6) MAXIMUM VDS BIAS (V) 130 130 104 78 52
Typical Performance Curves
Unless Otherwise Specified
LET = 26MeV/mg/cm2, RANGE = 43 LET = 37MeV/mg/cm2, RANGE = 36 LIMITING INDUCTANCE (HENRY) 140 120 100 VDS (V) 80 60 40 20 0 0 TEMP = 25oC -5 -10 -15 VGS (V) -20 -25 FLUENCE = 1E5 IONS/cm2 (TYPICAL)
1E-3
1E-4 ILM = 10A 30A 1E-5 100A 300A 1E-6
1E-7
10
30
100 DRAIN SUPPLY (V)
300
1000
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO IAS
4-3
FSYC163D, FSYC163R Typical Performance Curves
80
Unless Otherwise Specified
(Continued)
500 TC = 25oC
60 ID , DRAIN CURRENT (A)
100
ID , DRAIN (A)
100s
40
10
20
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
1ms
10ms
0
-50
0
50
100
150
1
1
10
100
300
TC , CASE TEMPERATURE (oC)
VDS , DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5 PULSE DURATION = 250ms, VGS = 12V, ID = 39A 2.0 NORMALIZED rDS(ON)
12V
QG
1.5
QGS VG
QGD
1.0
0.5
CHARGE
0.0 -80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 5. BASIC GATE CHARGE WAVEFORM
FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE
10
THERMAL RESPONSE (ZJC)
1 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 0.001 10-5 10-4 10-3 10-2 10-1 t1 t2 100 101
NORMALIZED
0.1
PDM
t, RECTANGULAR PULSE DURATION (s)
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
4-4
FSYC163D, FSYC163R Typical Performance Curves
1000 IAS , AVALANCHE CURRENT (A)
Unless Otherwise Specified
(Continued)
100 STARTING TJ = 150oC 10
STARTING TJ = 25oC
1 0.01
IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 0.1 1 10 tAV, TIME IN AVALANCHE (ms)
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L + CURRENT I TRANSFORMER AS BVDSS tP IAS 50 + VDD VDS VDD
-
VARY tP TO OBTAIN REQUIRED PEAK IAS VGS 20V
DUT 50V-150V 50 tAV
0V
tP
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
VDD
tON td(ON)
tOFF td(OFF) tr tf 90%
RL VDS VGS = 12V DUT 0V RGS
VDS
90%
10%
10%
90% VGS 10% 50% PULSE WIDTH 50%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
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FSYC163D, FSYC163R Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) TC = 25oC, Unless Otherwise Specified
PARAMETER Gate to Source Leakage Current Zero Gate Voltage Drain Current Drain to Source On Resistance Gate Threshold Voltage NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. SYMBOL IGSS IDSS rDS(ON) VGS(TH) TEST CONDITIONS VGS = 20V VDS = 80% Rated Value TC = 25oC at Rated ID ID = 1.0mA MAX 20 (Note 7) 25 (Note 7) 20% (Note 8) 20% (Note 8) UNITS nA A V
Screening Information
TEST Gate Stress Pind Pre Burn-In Tests (Note 9) Steady State Gate Bias (Gate Stress) Interim Electrical Tests (Note 9) Steady State Reverse Bias (Drain Stress) PDA Final Electrical Tests (Note 9) NOTE: 9. Test limits are identical pre and post burn-in. JANTXV EQUIVALENT VGS = 30V, t = 250s Optional MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours All Delta Parameters Listed in the Delta Tests and Limits Table MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 160 hours 10% MIL-S-19500, Group A, Subgroup 2 JANS EQUIVALENT VGS = 30V, t = 250s Required MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours All Delta Parameters Listed in the Delta Tests and Limits Table MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours 5% MIL-S-19500, Group A, Subgroups 2 and 3
Additional Screening Tests
PARAMETER Safe Operating Area Unclamped Inductive Switching Thermal Response Thermal Impedance SYMBOL SOA IAS VSD VSD TEST CONDITIONS VDS = 104V, t = 10ms VGS(PEAK) = 15V, L = 0.1mH tH = 10ms; VH = 25V; IH = 4A tH = 500ms; VH = 25V; IH = 4A Heat Sink Required MAX 4.0 186 55 115 UNITS A A mV mV
4-6
FSYC163D, FSYC163R Rad Hard Data Packages - Intersil Power Transistors
TXV Equivalent
1. RAD HARD TXV EQUIVALENT - STANDARD DATA PACKAGE
A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet D. Group A E. Group B F. Group C G. Group D - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet
Class S - Equivalents
1. RAD HARD "S" EQUIVALENT - STANDARD DATA PACKAGE
A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data F. Group A G. Group B H. Group C I. Group D - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet
2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA PACKAGE
A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet - Precondition Lot Traveler - Pre and Post Burn-In Read and Record Data D. Group A E. Group B - Attributes Data Sheet - Group A Lot Traveler - Attributes Data Sheet - Group B Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3) - Bond Strength Data (Subgroup B3) - Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6) - Attributes Data Sheet - Group C Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6) - Bond Strength Data (Subgroup C6) - Attributes Data Sheet - Group D Lot Traveler - Pre and Post RAD Read and Record Data
2. RAD HARD MAX. "S" EQUIVALENT - OPTIONAL DATA PACKAGE
A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups A2, A3, A4, A5 and A7 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups B1, B3, B4, B5 and B6 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups C1, C2, C3 and C6 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Pre and Post Radiation Data
F. Group C
G. Group D
G. Group B
H. Group C
I. Group D
4-7
FSYC163D, FSYC163R SMD2
3 PAD CERAMIC LEADLESS CHIP CARRIER
E
INCHES SYMBOL A b D MIN 0.129 0.135 0.520 0.435 0.115 0.685 0.470 0.152 MAX 0.139 0.145 0.530 0.445 0.125 0.695 0.480 0.162
MILLIMETERS MIN 3.27 3.43 13.20 11.05 2.92 17.40 11.94 3.86 MAX 3.53 3.68 13.46 11.30 3.17 17.65 12.19 4.11 NOTES -
D
D1 D2 E E1 E2 NOTES:
A
1. No current JEDEC outline for this package. 2. Controlling dimension: INCH. 3. Revision 2 dated 6-98.
E1 E2
2 3 D2
D1
1
b
1 - GATE 2 - SOURCE 3 - DRAIN
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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